Taiwanese media outlet Economic Daily News reported that TSMC has completed limited risk production of around 5,000 wafers using its 2nm process at the Baoshan fab in Hsinchu Science Park. Why it ...
One of the innovations involves the integration of the diffusion process, combining the doping of solar and the thermal oxidization of the wafers in a single step. Thermal oxidization of wafers is ...
The company also announced an even more ambitious technology named System-on-Wafer (SoW) that will allow for 3D stacking of logic and memory directly on top of a 300mm wafer-sized chip.
But there is a catch. TSMC's quote for a 300-mm wafer process using its N2 technology will exceed $30,000, according to the report. Previously it was expected that world's largest contract maker ...
The Recharged Czochralski (RCz) crystal growth process, which enables crucible re-use without powering down between pulls, is increasingly used to produce ingots for both n-type and p-type wafers ...
Let's rewind to 2013 and the A7, Apple's first 64-bit chip built on TSMC's 28nm process. At the time, those 28nm wafers cost Apple $5,000 each, according to Creative Strategies CEO Ben Bajarin's ...
The SB6/8e system features a rigid vacuum chamber for best-in-class post-bond alignment accuracy, independent upper and lower substrate heaters and precise programmable force control during the wafer ...